It has conventionally been thought that if a clock is stopped in a CMOS semiconductor integrated circuit, no consumption current flows. However, if a subthreshold current flows, even if the clock is stopped, consumption current flows. Thus, as a technique for reducing such subthreshold current in a standby state, a power gating technique has begun to be used widely. This power gating technique is for blocking power supply to internal circuits while maintaining an output node potential that needs to be held in a standby state.
U.S. Pat. No. 8,499,272 ('272 patent) discloses a semiconductor device that uses a power gating technique and that suppresses an increase in the resistance of power supply and ground lines. In the semiconductor device, a plurality of circuit cells are arranged in separate circuit cell shelves. More specifically, a plurality of circuit cells are divided into a group of circuit cells, each using a main power supply line (potential VPERI) and a pseudo-ground line (potential VSSZ). The plurality of circuit cells are further divided into a group of circuit cells each using a pseudo-power supply line (potential VPERIZ) and a main ground line (potential VSS). In this way, since the power supply and ground lines in each circuit cell shelf can have a larger interconnect width, an increase in the resistance of the power supply and ground lines is suppressed (see FIGS. 3 and 5 in the '272 patent).
However, in the semiconductor device disclosed in the '272, a functional circuit region and a driver region are separated from each other (see FIG. 3 in the '272 patent). Thus, there is a problem in that the layout regions for these elements are increased. In addition, regarding a circuit cell in the functional circuit region arranged far from the driver region, there can be a large distance (interconnect length) between the circuit cell and a Subthreshold Current Reduction Circuit (SCRC) driver. Thus, there is a problem that the interconnect resistance cannot be sufficiently suppressed. In this case, when the circuit cell is operated, the interconnect resistance causes waveform distortion in voltages of the power supply and ground lines, imposing a limit on improvement of the speed of a circuit operation in the semiconductor device.